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?2017 advanced linear devices, inc., vers. 1.2 www.aldinc.com 1 of 12 e epad tm ? n a b l e d e a daned l nea d ee n general description the ALD212908a/ALD212908 precision enhancement mode n-channel epad ? mosfet array is precision matched at the factory using ald?s proven epad ? cmos technology. these quad monolithic devices are enhanced additions to the ALD212908a/ALD212908 epad ? mosfet family, with increased forward transconductance and output conductance, particularly at very low supply volt- ages. intended for low voltage, low power small signal applications, the ALD212908a/ ALD212908 features precision threshold voltage, which enables circuit designs with input/output signals referenced to enhanced operating voltage ranges. with these devices, a circuit with multiple cascading stages can be built to operate at extremely low supply/bias voltage levels. for example, a nanopower input am- plifier stage operating at less than 1.0v supply voltage has been successfully built with these devices. ALD212908a epad mosfets feature exceptional matched pair electrical char- acteristics of gate threshold voltage v gs(th) set precisely at +0.80v + 0.01v, i ds = +20 a @ v ds = 0.1v, with a typical offset voltage of only + 0.001v (1mv). built on a single monolithic chip, they also exhibit excellent temperature track- ing characteristics. these precision devices are versatile as design components for a broad range of analog small signal applications such as basic building blocks for current mirrors, matching circuits, current sources, differential ampli- fier input stages, transmission gates, and multiplexers. they also excel in lim- ited operating voltage applications, such as very low level voltage-clamps and nano-power normally-on circuits. in addition to precision matched-pair electrical characteristics, each individual epad mosfet also exhibits well controlled manufacturing characteristics, en- abling the user to depend on tight design limits from different production batches. these devices are built for minimum offset voltage and differential thermal re- sponse, and they can be used for switching and amplifying applications in +0.1v to +10v ( + 0.05v to + 5v) powered systems where low input bias current, low input capacitance, and fast switching speed are desired. at v gs > +0.80v, the device exhibits enhancement mode characteristics whereas at v gs < +0.80v the device operates in the subthreshold voltage region and exhibits conven- tional sub threshold characteristics, with well controlled turn-off and sub-thresh- old levels that operate the same as standard enhancement mode mosfets. the ALD212908a/ALD212908 features high input impedance (2.5 x 10 10 ? ) and high dc current gain (>10 8 ). a sample calculation of the dc current gain at a drain output current of 30ma and input current of 300pa at 25 c is 30ma/300pa = 100,000,000, which translates into a dynamic operating current range of about eight orders of magnitude. a series of four graphs titled ?forward transfer char- acteristics?, with the 2 nd and 3 rd sub-titled ?expanded (subthreshold)? and ?fur- ther expanded (subthreshold)?, and the 4 th sub-titled ?low voltage?, illustrates the wide dynamic operating range of these devices. generally it is recommended that the v+ pin be connected to the most positive voltage and the v- and ic (internally-connected) pins to the most negative volt- age in the system. all other pins must have voltages within these voltage limits at all times. standard esd protection facilities and handling procedures for static sensitive devices are highly recommended when using these devices. precision n-channel epad ? mosfet array dual high drive matched pair features & benefits ? precision v gs(th) = +0.80v + 0.010v ? v os (v gs(th) match) to 2mv/10mv max. ? sub-threshold voltage (nano-power) operation ? < 800mv min. operating voltage ? < 1na min. operating current ? < 1nw min. operating power ? > 100,000,000:1 operating current ranges ? high transconductance and output conductance ? low r ds(on) of 14 ? ? output current > 50ma ? matched and tracked tempco ? tight lot-to-lot parametric control ? positive, zero, and negative v gs(th) tempco ? low input capacitance and leakage currents applications ? low overhead current mirrors and current sources ? zero power normally-on circuits ? energy harvesting circuits ? very low voltage analog and digital circuits ? zero power fail-safe circuits ? backup battery circuits & power failure detector ? extremely low level voltage-clamps ? extremely low level zero-crossing detector ? matched source followers and buffers ? precision current mirrors and current sources ? matched capacitive probes and sensor interfaces ? charge detectors and charge integrators ? high gain differential amplifier input stage ? matched peak-detectors and level-shifters ? multiple channel sample-and-hold switches ? precision current multipliers ? discrete matched analog switches/multiplexers ? nanopower discrete voltage comparators ALD212908a/ALD212908 v gs(th) = +0.08v *ic pins are internally connected, connect to v- sal, pal packages pin configuration ALD212908 v - g n1 d n1 s 12 d n2 g n2 1 2 3 6 7 8 4 5 m 1 m 2 v - v - v - ic* v + ordering information (?l? suffix denotes lead-free (rohs)) *contact factory for industrial temp. range or user-specified threshold voltage values. operating temperature range * 0 c to +70 c 8-pin soic package 8-pin plastic dip package ALD212908asal ALD212908apal ALD212908sal ALD212908pal
ALD212908a/ALD212908 advanced linear devices 2 of 12 notes: 1 consists of junction leakage currents operating electrical characteristics v + = +5v v - = gnd t a = 25 c unless otherwise specified ALD212908a ALD212908 parameter symbol min typ max min typ max unit test conditions gate threshold voltage v gs(th) 0.78 0.80 0.82 0.78 0.80 0.82 v i ds =20 a, v ds = 0.1v offset voltage v os 12 210mvv gs(th)m1 - v gs(th)m2 offset voltage tempco tc vos 55 v/ cv ds1 = v ds2 gatethreshold voltage tempco tc vgs(th) -1.7 -1.7 mv/ ci d = 20 a, v ds = 0.1v 0.0 0.0 i d = 760 a, v ds = 0.1v +0.6 +1.6 i d = 1.5 ma, v ds = 0.1v on drain current i ds(on) 79 79 ma v gs = +3.8v, v ds = +3v 85 85 av gs = +0.9v, v ds = +0.1v forward transconductance g fs 38 38 mmho v gs = +3.8v v ds = +3.0v transconductance mismatch ? g fs 1.8 1.8 % output conductance g os 2.3 2.3 mmho v gs = +3.8v v ds = +3.0v drain source on resistance r ds(on) 14 14 ? v gs = +5.8v v ds = +0.1v drain source on resistance r ds(on) 55k ? v gs = +0.8v, v ds = +0.1v 1.18 1.18 v gs = +0.9v, v ds = +0.1v drain source on resistance ? r ds(on) 1.8 1.8 % v gs = +5.8v tolerance v ds = +0.1v drain source on resistance ? r ds(on) 0.6 0.6 % mismatch drain source breakdown bv dsx 10 10 v v - = v gs = -0.2v voltage i ds = 10 a drain source leakage current 1 i ds(off) 10 400 10 400 pa v gs = -0.2v, v ds = +5v v - = -5v 44nat a = 125 c gate leakage current 1 i gss 5 200 5 200 pa v gs = +5v, v ds = 0v 11nat a = 125 c input capacitance c iss 30 30 pf transfer reverse capacitance c rss 22pf turn-on delay time t on 10 10 ns v + = 5v, r l = 5k ? turn-off delay time t off 10 10 ns v + = 5v, r l = 5k ? crosstalk 60 60 db f = 100khz absolute maximum ratings drain-source voltage, v ds 10.6v gate-source voltage, v gs 10.6v operating current 80ma power dissipation 500mw operating temperature range sal, pal 0 c to +70 c storage temperature range -65 c to +150 c lead temperature, 10 seconds +260 c caution: esd sensitive device. use static control procedures in esd controlled environment.
ALD212908a/ALD212908 advanced linear devices 3 of 12 performance characteristics of epad ? precision matched pair mosfet family ald2108xx/ald2129xx/ald2148xx/ald2169xx high precision monolithic quad/dual n-channel mosfet arrays are enhanced versions of the ald1108xx/ald1109xx epad ? mosfet family, with increased forward transconductance and output conductance, in- tended for operation at very low power supply voltages. these de- vices are also capable of sub-threshold operation with less than 1na of operating supply currents and at the same time delivering higher output drive currents (typ. > 50ma). they feature precision gate offset voltages, v os , defined as the difference in v gs(th) between mosfet pairs m1 and m2 or m3 and m4. ald's electrically programmable analog device (epad ? ) technol- ogy provides the industry's only family of matched mosfet tran- sistors with a range of precision gate-threshold voltage values. all members of this family are designed and actively programmed for exceptional matching of device electrical and temperature charac- teristics. gate threshold voltage v gs(th) values range from -3.50v depletion mode to +3.50v enhancement mode devices, including standard products with v gs(th) specified at -3.50v, -1.30v, -0.40v, +0.00v, +0.20v, +0.40v, +0.80v, +1.40v, and +3.30v. ald can also provide any customer-desired v gs(th) between -3.50v and +3.50v on a special order basis. for all these devices ald epad technology enables excellent well-controlled gate threshold volt- age, subthreshold voltage, and low leakage characteristics. with well matched design and precision programming, units from differ- ent production lots provide the user with exceptional matching and uniformity characteristics. built on the same monolithic ic chip, the units also have excellent temperature tracking characteristics. this ald2108xx/ald2129xx/ald2148xx/ald2169xx epad mosfet array product family (epad mosfet) is available in three separate categories, each providing a distinctly different set of elec- trical specifications and characteristics. the first category is the ald210800a/ald210800/ald212900a/ald212900 zero-thresh- old? mode epad mosfets. the second is the ald2108xx/ ald2129xx enhancement mode epad mosfets. the third cat- egory includes the ald2148xx/ald2169xx depletion mode epad mosfets. (the suffix ?xx? denotes threshold voltage in 0.1v steps, for example, xx=08 denotes 0.80v). for each device, there is a zero-tempco bias current and bias voltage point. when a design utilizes such a feature, then the gate-threshold voltage is tempera- ture stable, greatly simplifying certain designs where stability of certain circuit parameters over a temperature range is desired. the ald210800a/ald210800 are quad zero threshold mosfets in which the individual gate-threshold voltage of each mosfet is set at zero, v gs(th) = 0.00v at i ds(on) = 10 a @ v ds(on) = +0.1v (i ds(on) = 20 a for the dual ald212900a/ald212900). zero threshold mosfets operate in the enhancement region when op- erated above threshold voltage (v gs > 0.00v and i ds > 10 a) and subthreshold region when operated at or below threshold voltage (v gs 0.00v and i ds < 10 a). these devices, along with other low v gs(th) members of the product family, enable ultra low supply voltage analog or digital operation and nanopower circuit designs, thereby reducing or eliminating the use of very high valued (expen- sive) resistors in many cases. the ald2108xx/ald2129xx (quad/dual) product family features precision matched enhancement mode epad mosfet devices, which require a positive gate bias voltage v gs to turn on. precision v gs(th) values at +3.30v, +1.40v, +0.80v, +0.40v and +0.20v are offered. no conductive channel exists between the source and drain at zero applied gate voltage (v gs = 0.00v) for +3.30v, +1.40v and +0.80v versions. the +0.40v and the +0.20v versions have a sub- threshold current at about 1na and 100na for the ald2108xx (2na and 200na for the ald2129xx) respectively at zero applied gate voltage. they are also capable of delivering lower r ds(on) and higher output currents greater than 68ma (see specifications). the ald2148xx/ald2169xx (quad/dual) features depletion mode epad mosfets, which are normally-on devices at zero applied gate voltage. the v gs(th) is set at a negative voltage level (v- < v gs < v s ) at which the epad mosfet turns off. without a supply voltage and/or with v gs = v- = 0.00v = ground, the epad mosfet device is already turned on and exhibits a defined and controlled on-resistance r ds(on) . an epad mosfet may be turned off when a negative voltage is applied to v- pin and v gs set more negative than its v gs(th) . these depletion mode epad mosfets are different from most other depletion mode mosfets and jfets in that they do not exhibit high gate leakage currents and channel/junction leakage currents, while they stay controlled, modulated and turned off at precise voltages. the same mosfet device equations as those for enhancement mode devices apply. key application environments epad mosfets are ideal for circuits requiring low v os and low operating currents with tracked differential thermal responses. they feature low input bias currents (less than 200pa max.), low input capacitance and fast switching speed. these and other operating characteristics offer unique solutions in one or more of the follow- ing operating environments: * low supply voltage: 0.1v to 10v ( + 0.05v to + 5v) * ultra low supply voltage: < + 10mv to + 0.1v * nanopower operation: voltage x current = nw or w * precision v os characteristics * matching and tracking of multiple mosfets * matching across multiple packages electrical characteristics the turn-on and turn-off electrical characteristics of the epad mosfet products are shown in the i ds(on) vs. v ds(on) and i ds(on) vs. v gs graphs. each graph shows i ds(on) versus v ds(on) characteristics as a function of v gs in a different operating region under different bias conditions, while i ds(on) at a given gate input voltage is controlled and predictable. a series of four graphs titled ?forward transfer characteristics?, with the 2 nd and 3 rd sub-titled ?expanded (subthreshold)? and ?further expanded (subthreshold)?, and the 4 th sub-titled ?low voltage?, illustrates the wide dynamic operating range of these devices. classic mosfet equations for an n-channel mosfet also apply to epad mosfets. the drain current in the linear region (v ds(on) < v gs - v gs(th) ) is given by: i ds(on) = u . c ox . w/l . [v gs - v gs(th) - v ds /2] . v ds(on) where: u = mobility c ox = capacitance / unit area of gate electrode v gs = gate to source voltage v gs(th) = gate threshold (turn-on)voltage v ds(on) = drain to source on voltage w = channel width l = channel length in this region of operation the i ds(on) value is proportional to the v ds(on) value and the device can be used as a gate-voltage con- trolled resistor. for higher values of v ds(on) where v ds(on) v gs - v gs(th) , the saturation current i ds(on) is now given by (approx.): i ds(on) = u . c ox . w/l . [v gs - v gs(th) ] 2
ALD212908a/ALD212908 advanced linear devices 4 of 12 performance characteristics of epad? precision matched pair mosfet family (cont.) sub-threshold region of operation the gate threshold (turn-on) voltage v gs(th) of the epad mosfet is a voltage below which the mosfet conduction channel rapidly turns off. for analog designs, this gate threshold voltage directly affects the operating signal voltage range and the operating bias current levels. at a voltage below v gs(th) , an epad mosfet exhibits a turn-off characteristic in an operating region called the subthreshold re- gion. this is when the epad mosfet conduction channel rapidly turns off as a function of decreasing applied gate voltage. the con- duction channel, induced by the gate voltage on the gate elec- trode, decreases exponentially and causes the drain current to de- crease exponentially as well. however, the conduction channel does not shut off abruptly with decreasing gate voltage, but rather de- creases at a fixed rate of about 104mv per decade of drain current decrease. for example, for the ald2108xx device, if the gate thresh- old voltage is +0.20v, the drain current is 10 a at v gs = +0.20v. at v gs = +0.096v, the drain current would decrease to 1 a. ex- trapolating from this, the drain current is about 0.1 a at v gs = 0.00v, 1na at v gs = -0.216v, and so forth. this subthresh- old characteristic extends all the way down to current levels below 1na and is limited by junction leakage currents. at a drain current of ?zero current? as defined and selected by the user, the v gs voltage at that zero current can now be estimated. note that using the above example, with v gs(th) = +0.20v, the drain current still hovers around 100na when the gate is at ground voltage. with a device that has v gs(th) = +0.40v (part number ald210804), the drain current is about 2na when the gate is at ground potential. thus, in this case an input signal referenced to ground can operate with a natural drain current of only 2na internal bias current, dissipating nano-watts of power. low power and nanopower when supply voltages decrease, the power consumption of a given load resistor decreases as the square of the supply voltage. thus, one of the benefits in reducing supply voltage is to reduce power consumption. while decreasing power supply voltages and power consumption go hand-in-hand with decreasing useful ac bandwidth and increased noise effects in the circuit, a circuit designer can make the necessary tradeoffs and adjustments in any given circuit design and bias the circuit accordingly for optimal performance. with epad mosfets, a circuit that performs any specific function can be designed so that power consumption of that circuit is mini- mized. these circuits operate in low power mode where the power consumed is measure in mw, w, and nw (nano-watt) region and still provide a useful and controlled circuit function operation. zero temperature coefficient (ztc) operation for an epad mosfet in this product family, operating points exist where the various factors that cause the current to increase as a function of temperature balance out those that cause the current to decrease, thereby canceling each other, and resulting in a net tem- perature coefficient of near zero. an example of this temperature stable operating point is obtained by a ztc voltage bias condition, which is 0.38v above v gs(th) when v ds(on) = +0.1v, resulting in a temperature stable current level of about 380 a for the ald2108xx and 760 a for the ald2129xx devices. performance characteristics performance characteristics of the epad mosfet product family are shown in the following graphs. in general, the gate threshold voltage shift for each member of the product family causes other affected electrical characteristics to shift linearly with v gs(th) bias voltage. this linear shift in v gs causes the subthreshold i-v curves to shift linearly as well. accordingly, the subthreshold operating cur- rent can be determined by calculating the gate source voltage drop relative to its gate threshold voltage, v gs(th) . normally-on fixed r ds(on) at v gs = ground several members of this mosfet family produce a fixed resis- tance when their gate is grounded. for ald210800, the drain cur- rent at v ds = 0.1v is @ 10 a at v gs = 0.00v. thus, just by ground- ing the gate of the ald210800, a resistor with r ds(on) = ~10k ? is produced (for ald212900 device, r ds(on) = ~5k ? ). when an ald214804 gate is grounded, the drain current i ds = 424 a @ v ds = 0.1v, producing r ds(on) = ~236 ? . similarly, ald214813 and ald214835 produces 1.71ma and 3.33ma for each mosfet, respectively, at v gs = 0.00v, producing r ds(on) values of 59 ? and 30 ? , respectively. for example, when all 4 mosfets in an ald214835 are connected in parallel, an on-resistance of 30/4 = ~7.5 ? is measured between the drain and source terminals when v gs = v- = 0.00v, producing a fixed on-resistance without any gate bias voltages applied to the device. matching characteristics one of the key performance benefits of using matched-pair epad mosfets is to maintain temperature tracking between the differ- ent devices in the same package. in general, for epad mosfet matched pair devices, one device of the matched pair has gate leakage currents, junction temperature effects, and drain current temperature coefficient as a function of bias voltage that cancel out similar effects of the other device, resulting in a temperature stable circuit. as mentioned earlier, this temperature stability can be fur- ther enhanced by biasing the matched-pairs at zero tempco (ztc) point, even though that may require special circuit configurations and power consumption design considerations. power supply sequences and esd control epad mosfets are robust and reliable, as demonstrated by more than a decade of production history supplied to a large installed base of customers across the world. however, these devices do require a few design and handling precautions in order for them to be used successfully. epad mosfets, being a cmos integrated circuit, in addition to having drain, gate and source pins normally found in a mosfet device, have three other types of pins, namely v+, v- and ic pins. v+ is connected to the substrate, which must always be connected to the most positive supply in a circuit. v- is the body of the mosfet, which must be connected to the most negative supply voltage in the circuit. ic pins are internally connected pins, which must also be connected to v-. drain, gate and source pins must have volt- ages between v- and v+ at all times. proper power-up sequencing requires powering up supply voltages before applying any signals. during the power down cycle, remove all signals before removing v- and v+. this way internally back biased diodes are never allowed to become forward biased, possi- bly causing damage to the device. of course, standard esd con- trol procedures should also be observed so that static charge does not degrade the performance of the devices.
ALD212908a/ALD212908 advanced linear devices 5 of 12 typical performance characteristics forward transfer characteristics low voltage 500 400 300 200 0 100 gate source overdrive voltage v gs - v gs ( th ) (v) drain source on current i ds(on) ( a) 0 +0.1 +0.2 +0.4 +0.5 +0.3 -0.4 -0.3 -0.1 -0.2 v ds = + 5.0v t a = + 25 c forward transfer characteristics further expanded (subthreshold) gate source overdrive voltage v gs - v gs(th) (v) drain source on current i ds(on) (na) 1000000.00 10000.00 1000.00 100.00 10.00 1.00 0.10 0.01 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 +0.1 +0.2 100000.00 t a = + 25 c low voltage output characteristics drain source on voltage - v ds(on) (v) drain source on current i ds(on) (ma) -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 40 30 20 10 0 -10 -20 -30 -40 v- = 0v 1v 2v 4v 5v v gs - v gs(th) = 0.5v 3v output characteristics drain source on voltage - v ds(on) (v) drain source on current i ds(on) (ma) 0 2 40 100 80 60 20 0 6 8 10 4 v gs= v gs(th) +0.5v v gs= v gs(th) +1.0v v gs= v gs(th) +2.5v v gs= v gs(th) +3.0v v gs= v gs(th) +1.5v v gs= v gs(th) +2.0v forward transfer characteristics 100 drain source on current i ds(on) (ma) gate source voltage - v gs (v) -4 0 60 0 -2 24 6 8 20 80 40 t a = + 25 c v ds = + 5v v gs(th) = +0.4v v gs(th) = -3.5v v gs(th) = +1.4v v gs(th) = -0.4v v gs(th) = 0.0v v gs(th) = +0.2v v gs(th) = -0.8v v gs(th) = -0.2v v gs(th) = +0.8v v gs(th) = -1.3v forward transfer characteristics expanded (subthreshold) gate source voltage - v gs (v) drain source on current i ds(on) (na) 100000.00 10000.00 1000.00 100.00 10.00 1.00 0.10 0.01 -5 -4 -3 -2 -1 0 +1 +2 1000000.00 ald216935 ald212914 ALD212908 ald212904 ald216904 ald216908 ald216913 ald216902 ald212900 ald212902 t a = + 25 c
ALD212908a/ALD212908 advanced linear devices 6 of 12 typical performance characteristics (cont.) low level output conductance vs. ambient temperature 1000 800 600 400 200 0 low level output conductance - g os ( a/v) ambient temperature - t a ( c) -50 -25 0 +25 +50 +125 +100 +75 v gs = v gs(th) + 0.5v v ds = + 3.0v high level output conductance vs. gate threshold voltage gate threshold voltage - v gs(th) (v) -4.0 -3.0 -2.0 -1.0 0.0 +2.0 +3.0 +1.0 high level output conductance - g os (ma/v) 2.75 2.50 2.00 2.25 1.75 1.50 v gs = v gs(th) + 3.0v v ds = + 3.0v t a = + 25 c low level output conductance vs. gate threshold voltage 1000 0 low level output conductance - g os ( a/v) -3.0 -2.0 -1.0 0 +2.0 +3.0 +1.0 -4.0 200 400 600 800 gate threshold voltage - v gs(th) (v) t a = + 25 c v gs = v gs(th) + 0.5v v ds = + 3.0v high level output conductance vs. ambient temperature 3.50 3.00 2.75 high level output conductance - g os (ma/v) -50 -25 0 +25 +50 +125 +100 +75 3.25 2.50 2.00 2.25 ambient temperature - t a ( c) v gs = v gs(th) + 3.0v v ds = + 3.0v transconductance vs. ambient temperature transconductance g fs (ma/v) 100 80 60 40 0 20 ambient temperature - t a ( c) -50 -25 0 +25 +50 +125 +100 +75 v gs = v gs(th) + 3.0v v ds = + 3.0v transconductance vs. gate threshold voltage gate threshold voltage - v gs(th) (v) -4.0 -3.0 -2.0 -1.0 0.0 +2.0 +3.0 +1.0 80 60 40 20 transconductance g fs ( ma/v) 0 t a = +25 c v gs = v gs(th) + 3.0v v ds = 3.0v
ALD212908a/ALD212908 advanced linear devices 7 of 12 typical performance characteristics (cont.) output characteristics drain source on voltage - v ds(on) (v) 100 80 60 40 20 0 drain source on current i ds(on) (ma) 5 4 3 2 1 0 v gs = v gs(th) + 3v +125 c +70 c -55 c +25 c 0 c zero temperature coefficient (ztc) gate source overdrive voltage v gs - v gs(th) (v) 1000 600 0 +0.3 +0.5 0 +0.4 +0.2 +0.1 drain source on current i ds(on) ( a) 800 400 200 +125 c - 55 c +25 c v ds = + 0.1v zero temperature coefficient (ztc) gate source overdrive voltage vs. drain source on current 0 10 20 30 40 70 60 50 drain source on current - i ds(on) (ma) gate source overdrive voltage v gs- v gs(th) (v) 4 3 2 5 1 0 +125 c +25 c +70 c -55 c 0 c v+ = v ds = + 5v gate threshold voltage vs. ambient temperature 2.0 0 gate threshold voltage v gs(th) (v) ambient temperature - t a ( c) -50 -25 0 +25 +50 +125 +100 +75 -1.0 -2.0 1.0 v ds = + 0.1v i d = 20 a v gs(th) = 0.8v v gs(th) = 0.0v v gs(th) = -1.4v drain source on current vs. gate source overdrive voltage 100 80 60 40 20 0 5 4 3 2 1 0 drain source on current i ds(on) (ma) gate source overdrive voltage v gs - v gs(th) (v) v ds = + 1.0v -55 c +25 c +70 c +125 c 0 c 5 4 3 2 1 0 10 8 6 4 2 0 gate source overdrive voltage vs. drain source on current gate source overdrive voltage v gs- v gs(th) (v) drain source on current - i ds(on) (ma) v ds = + 0.1v +25 c - 55 c 0 c +125 c +70 c
ALD212908a/ALD212908 advanced linear devices 8 of 12 typical performance characteristics (cont.) offset voltage vs. ambient temperature +10 +8 +6 +4 +2 -2 0 -10 offset voltage v os (mv) -50 -25 0 +25 +50 +125 +100 +75 ambient temperature - t a ( c) -8 -6 -4 representative units v os = v gs(th) m1 - v gs(th) m2 drain off leakage current i ds(off) vs. ambient temperature ambient temperature - t a ( c) -50 -25 0 +25 +50 +125 +100 +75 500 400 drain off leakage current i ds(off) (pa) 300 200 600 100 0 i ds(off)
ALD212908a/ALD212908 advanced linear devices 9 of 12 differential amplifier current source multiplication current source mirror current source with gate control typical applications i set r set m 3 v + = +5v i source m 1 , m 2 : n - channel mosfet m 3 , m 4 : p - channel mosfet m 1 m 2 v + = +5v m 4 m3, m4: ald1102, ald1117, 1/2 ald1103, 1/2 ald1105, 1/2 ald1107, or 1/2 ald3107xx m1, m2: ald1101, ald1116, ald1109xx, ald2129xx, 1/2 ald1103, 1/2 ald1105, 1/2 ald1106, 1/2 ald1108xx, or 1/2 ald2108xx r source i source = i set = v + - vt r set where vt = v gs - v gs(th) = v ds v + = +5v i source r set m 3 i set on off digital logic control of current source m 1 : n - channel mosfet m 3, m 4 : p - channel mosfet m 4 m 1 r source m1: 1/2 ald1101, 1/2 ald1116, 1/2 ald1109xx, 1/2 ald2129xx, 1/4 ald1103, 1/4 ald1105, 1/4 ald1106, 1/4 ald1108xx, or 1/4 ald2108xx m3, m4: ald1102, ald1117, 1/2 ald1103, 1/2 ald1105, 1/2 ald1107, or 1/2 ald3107xx v + pmos pair m 4 v out v in - nmos pair m 2 m 1 v in + current source m 3 m 1 , m 2 : n - channel mosfet m 3 , m 4 : p - channel mosfet m3, m4: ald1102, ald1117, 1/2 ald1103, 1/2 ald1105, 1/2 ald1107, or 1/2 ald3107xx m1, m2: ald1101, ald1116, ald1109xx, ald2129xx, 1/2 ald1103, 1/2 ald1105, 1/2 ald1106, 1/2 ald1108xx, or 1/2 ald2108xx m set, m 1 ..m n : n - channel mosfet i set v + = +5v i source = i set x n r set m 2 m 3 m set m 1 m n package 1 package n mset, m1..mn: n x ald1101, n x ald1116, n x ald1109xx, n x ald2129xx, n x ald1103, n x ald1106, n x ald1108xx, or n x ald2108xx all m's in the set are from the same part number. v + = +5v r source
ALD212908a/ALD212908 advanced linear devices 10 of 12 cascode current sources basic current sources p- channel current source n- channel current source typical applications (cont.) i set v + = +5v m 2 i source r set m 3 m 1 m 1 , m 2 , m 3 , m 4 : n - channel mosfet where m1 and m2 is a matched pair and m3 and m4 is a second matched pair. m 4 m1, m2: ald1101, ald1116, ald2129xx, 1/2 ald1103, 1/2 ald1105, 1/2 ald1106, or 1/2 ald2108xx v + = +5v r source m3, m4: ald1101, ald1116, 1/2 ald1103, 1/2 ald1105, 1/2 ald1106, or 1/2 ald2108xx i source v + = +5v r set i set 1 2 3 m 1 5 6 8 m 2 7 m 1 , m 2 :n - channel mosfet v + = +5v r source m1, m2: ald1101, ald1116, ald1109xx, ald2129xx, 1/2 ald1103, 1/2 ald1105, 1/2 ald1106, 1/2 ald1108xx, or 1/2 ald2108xx i source = i set = v + - vt r set where vt = v gs - v gs(th) = v ds v + = +5v 2 3 5 6 7 8 m 4 i source m 3 r set i set m 3 , m 4 : p - channel mosfet r source m3, m4: ald1102, ald1117, 1/2 ald1103, 1/2 ald1105, 1/2 ald1107, or 1/2 ald3107xx i set v + = +5v m 1 m 3 m 2 m 4 i source r set m 1 , m 2 , m 3 , m 4 : p - channel mosfet where m1 and m2 is a matched pair and m3 and m4 is a second matched pair. i source = i set = v + - 2vt r set where vt = v gs - v gs(th) = v ds r source m1, m2: ald1102, ald1117, 1/2 ald1103, 1/2 ald1105, 1/2 ald1107, or 1/2 ald3107xx m3, m4: ald1102, ald1117, 1/2 ald1103, 1/2 ald1105, 1/2 ald1107, o r 1/2 ald3107xx
ALD212908a/ALD212908 advanced linear devices 11 of 12 8 pin plastic soic package millimeters inches min max min max dim a a 1 b c d-8 e e h l s 1.75 0.25 0.45 0.25 5.00 4.05 6.30 0.937 8 0.50 0.053 0.004 0.014 0.007 0.185 0.140 0.224 0.024 0 0.010 0.069 0.010 0.018 0.010 0.196 0.160 0.248 0.037 8 0.020 1.27 bsc 0.050 bsc 1.35 0.10 0.35 0.18 4.69 3.50 5.70 0.60 0 0.25 ? soic-8 package drawing l c h s (45 ) ? e a a 1 b d s (45 ) e
ALD212908a/ALD212908 advanced linear devices 12 of 12 8 pin plastic dip package millimeters inches min max min max dim a a 1 a 2 b b 1 c d-8 e e 1 e e 1 l s-8 ? 3.81 0.38 1.27 0.89 0.38 0.20 9.40 5.59 7.62 2.29 7.37 2.79 1.02 0 5.08 1.27 2.03 1.65 0.51 0.30 11.68 7.11 8.26 2.79 7.87 3.81 2.03 15 0.105 0.015 0.050 0.035 0.015 0.008 0.370 0.220 0.300 0.090 0.290 0.110 0.040 0 0.200 0.050 0.080 0.065 0.020 0.012 0.460 0.280 0.325 0.110 0.310 0.150 0.080 15 pdip-8 package drawing b 1 s b e e 1 d e a 2 a 1 a l c e 1 ?

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